I am seeking guidance to explore opportunities in VLSI design, leveraging my experience as a VLSI Trainee. Skilled in physical design, RTL development, and EDA tools like Cadence Virtuoso and Synopsys ICC2 Shell, I have executed Place-and-Route (PnR) flows, ensuring timing closure and validations through DRC, LVS, and STA. My projects, including full adder design and CMOS inverter analysis, reflect my ability to optimize designs. I’m eager to contribute to innovative semiconductor projects.

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